GaN FET TO‑247 for Servo Drive Inverters: GLIT‑RGN65C035 (650V)

1. Product Overview

Summary:
GLIT‑RGN65C035 targets high‑efficiency servo drives and industrial motor inverters that need 650 V blocking capability, low RDS(on), and low switching charge in a standard TO‑247 footprint.

• Supplier: Jiangsu Guanlong Integrated Technology Co., Ltd.
• Device type: 650 V Super‑GaN FET
• Package: TO‑247, GSD pin layout
• Target application: 3‑phase servo drive inverters and other motor‑control power stages

[Jiangsu Guanlong Integrated Technology Co., Ltd.]

2. Quick Electrical Specifications (At a Glance)

Summary:
This section consolidates the key electrical ratings and package information that servo drive designers typically check first.

2.1 Key Parameters

2.2 Package and Pin Layout

The GLIT‑RGN65C035 uses a TO‑247 package with a GSD (Gate–Source–Drain) pin layout, which is highlighted as being favorable for high‑speed layout and reduced loop inductance.

3. Why GLIT‑RGN65C035 Fits Servo Drive Inverter Power Stages

Summary:
Servo drive inverters benefit from fast, efficient switching, low conduction losses, and predictable commutation behavior. GLIT‑RGN65C035’s RDS(on), Qg, Qrr, and GSD pin layout are aligned with these requirements.

3.1 Fast Switching with Low Gate Charge

Servo drives often operate at higher switching frequencies (within EMI and device‑stress limits) to reduce current ripple and improve control bandwidth.

• GLIT‑RGN65C035 lists a typical gate charge Qg of 28 nC, which reduces:
  • Required gate driver current
  • Switching losses at a given frequency
• Lower Qg is especially important in 3‑phase inverters where multiple devices switch per PWM cycle.

3.2 Low Conduction Losses for Inverter Leg Currents

For 3‑phase servo inverters, RMS phase current can be significant, especially in high‑torque or continuous‑duty applications.

• GLIT‑RGN65C035 specifies RDS(on) (max) = 41 mΩ.
• Lower RDS(on) helps reduce:
  • Conduction losses in each inverter leg
  • Junction temperature rise at high load
  • Heatsink and cooling requirements for a given output power

The combination of 650 V rating and 41 mΩ max RDS(on) in a TO‑247 package is typically suitable for medium‑power servo drives when paired with appropriate thermal design.

3.3 Commutation and Reverse Recovery Behavior

Motor inverters commutate current frequently, especially under field‑oriented control (FOC) or vector control.

• GLIT‑RGN65C035 lists:
  • Qrr (typ): 175 nC
  • A statement that “no free‑wheeling diode [is] required” for some use cases (per device information).

Lower reverse recovery charge and GaN’s intrinsic behavior can reduce:

• Commutation losses
• Switching stress during diode reverse recovery
• EMI associated with hard commutation events

However, external diode omission is topology‑ and design‑dependent.

Designers should:

1. Evaluate commutation waveforms on the actual inverter hardware.
2. Verify that voltage overshoot and current spikes remain within device limits.
3. Confirm that EMI and thermal margins are acceptable without external diodes.

3.4 High‑Speed‑Friendly GSD Pin Layout

The GSD pin layout is called out as an advantage for high‑speed design:

• GSD pin arrangement can:
  • Reduce gate‑loop inductance
  • Improve switching waveform quality
  • Support higher dV/dt and dI/dt with better control

This is particularly important in servo drive inverters, where:

• PCB layout quality has a strong impact on EMI and ringing.
• Designers often need to balance switching speed against noise and overshoot.

3.5 Typical Use in a 3‑Phase Servo Drive Inverter

In a standard 3‑phase servo drive inverter:

• The topology is a 6‑switch bridge (three phase legs: U, V, W).
• GLIT‑RGN65C035 would typically be used as:
  • High‑side switch in each phase leg
  • Low‑side switch in each phase leg

Key ratings relevant to inverter topology:

• VDSS: 650 V
• VTDS (max transient): 800 V
• VGSS: ±18 V
• ID continuous:
  • 50 A @ TC = 25°C
  • 31.5 A @ TC = 100°C
• IDM (pulsed): 240 A (10 µs pulse width)

These values help determine:

• Maximum DC bus voltage and derating strategy
• Maximum phase current and overload capability
• Safe operating area (SOA) under transient and fault conditions

4. Thermal Performance for Compact Servo Drives

Summary:
Thermal design in servo drive inverters depends heavily on heatsinking, TIM, mounting conditions, and ambient environment. GLIT‑RGN65C035 provides baseline thermal resistance data for junction‑to‑case and junction‑to‑ambient.

4.1 Thermal Resistance Data

Provided thermal resistance values:

• RθJC (typ): 0.7 °C/W (junction‑to‑case)
• RθJA (typ): 40 °C/W (junction‑to‑ambient)

These figures are typically measured under standardized conditions and are used as inputs to loss and temperature calculations.

4.2 Practical Thermal Considerations

In real servo drive enclosures, actual thermal performance depends on:

• Heatsink size, material, and orientation
• Mounting pressure and contact quality
• Thermal interface material (TIM) properties and thickness
• Airflow (natural convection vs. forced air)
• PCB copper area and thermal spreading design

Designers should:

1. Estimate conduction + switching losses using worst‑case RDS(on) and switching energy.
2. Use RθJC 0.7 °C/W in combination with heatsink performance to estimate junction temperature.
3. Verify thermal behavior on hardware under continuous and overload operating points.

5. Key Specifications Summary

Summary:
This section consolidates core device information for quick reference or for use in design documents and BOMs.

• Supplier: Jiangsu Guanlong Integrated Technology Co., Ltd.
• Model Number: GLIT‑RGN65C035
• Device: 650 V Super‑GaN FET
• Package: TO‑247
• Pin Layout: GSD

Electrical Ratings:

• VDS (min): 650 V
• VTDS (max transient): 800 V
• RDS(on) (max): 41 mΩ
• Qg (typ): 28 nC
• Qrr (typ): 175 nC
• VGSS: ±18 V
• ID (continuous): 50 A @ TC = 25°C; 31.5 A @ TC = 100°C
• IDM (pulsed): 240 A (10 µs pulse width)
• TJ operating range: −55°C to +150°C

6. Design Checklist for Servo Inverter Implementation

Summary:
Use this checklist as a starting point when designing a servo drive inverter with GLIT‑RGN65C035. It focuses on safe operating limits, layout, and thermal design.

1. Gate Voltage Limits

   • Keep VGSS within ±18 V max, including any overshoot or ringing.
   • Verify gate driver compatibility with GaN FET gate requirements.

2. Gate Loop Layout

   • Minimize gate‑loop inductance.
   • Place the gate driver as close as practical to the GLIT‑RGN65C035.
   • Keep the gate‑return (source reference) path tight and low‑inductance.

3. Switching Node Voltage Stress

   • Validate switching‑node ringing on the actual PCB.
   • Ensure VDS remains within 650 V steady‑state and 800 V transient limits under worst‑case operating conditions.

4. Thermal Design

   • Calculate conduction + switching losses over the expected duty cycle and load profile.
   • Size heatsinking using your measured losses and RθJC = 0.7 °C/W, combined with case‑to‑ambient performance.
   • Confirm that junction temperature stays within the −55°C to +150°C range with appropriate margin.

5. Free‑Wheeling and Commutation Strategy

   • Treat the statement “no free‑wheeling diode required” as design‑dependent.
   • Confirm commutation behavior, reverse recovery losses, and EMI on your inverter hardware.
   • Decide whether additional diodes or snubbers are required based on measured data.

6. System‑Level Validation

   • Verify efficiency, thermal behavior, and EMI at:
     • Rated load
     • Overload conditions
     • Worst‑case ambient temperatures

7. FAQ: GLIT‑RGN65C035 for Servo Drive Inverters

Summary:
This FAQ addresses common design and selection questions for GLIT‑RGN65C035 in servo drive and motor‑control applications.

Q1: What is GLIT‑RGN65C035?

GLIT‑RGN65C035 is a 650 V Super‑GaN FET in a TO‑247 package with GSD pin layout, supplied by Jiangsu Guanlong Integrated Technology Co., Ltd.
It is designed for fast, efficient power switching in applications such as servo drive inverters and other motor‑control power stages.

Q2: Why use a GaN FET TO‑247 in a servo drive inverter?

Servo inverters benefit from low switching and conduction losses to improve efficiency and reduce thermal stress.
GLIT‑RGN65C035 lists Qg (typ) = 28 nC, RDS(on) (max) = 41 mΩ, and Qrr (typ) = 175 nC, which are key parameters for:

• Reducing switching losses at higher PWM frequencies
• Lowering conduction losses in each inverter leg
• Improving overall system power density and cooling requirements

Q3: What are the key voltage and gate limits of GLIT‑RGN65C035?

The key limits (per provided ratings) are:

• VDSS: 650 V
• VTDS (max transient): 800 V
• VGSS: ±18 V

Designers must ensure that bus voltage, overshoot, and gate drive remain within these limits under all operating and fault conditions.

Q4: Is GLIT‑RGN65C035 suitable for high‑frequency switching?

GLIT‑RGN65C035 has a typical gate charge of 28 nC and a typical reverse recovery charge of 175 nC, which support fast, efficient switching compared to many silicon MOSFETs of similar voltage rating.
Actual usable switching frequency depends on your gate driver, layout quality, EMI constraints, and thermal limits.

Q5: What thermal performance can I expect from GLIT‑RGN65C035?

The device provides:

• RθJC (typ): 0.7 °C/W (junction‑to‑case)
• RθJA (typ): 40 °C/W (junction‑to‑ambient)

Real‑world junction temperature depends on losses, heatsink design, TIM, and airflow. Designers should combine these values with measured losses to verify thermal margins in the target servo drive enclosure.

Q6: Who is the manufacturer of GLIT‑RGN65C035?

GLIT‑RGN65C035 is manufactured and supplied by Jiangsu Guanlong Integrated Technology Co., Ltd., a provider of Super‑GaN FETs and related power semiconductor devices.

[contact Jiangsu Guanlong Integrated Technology technical support]